This application relates generally to signal synthesis and more specifically to generating sinusoidally varying signals, such as sine and cosine wave signals, using a numerically controlled oscillator.
Numerically controlled oscillators (NCOs) are commonly employed in electronic systems requiring periodic signal references. Modulators and demodulators are examples of electronic systems that often require periodic signals and periodic signal generators, such as NCOs. Modulation includes processes in which an information signal is superimposed onto a carrier wave, such as a sinusoidally varying signal generated by an NCO. Well known analog modulation techniques include, for example, amplitude modulation (AM), frequency modulation (FM), and phase modulation (PM) among others. Well known digital modulation techniques include, for example, pulse amplitude modulation (PAM) and pulse width modulation (PWM) among others. Once modulated, carrier waves are transmitted to a receiver; at the receiver location, the information signal superimposed onto the carrier wave is extracted via a demodulation process in a demodulator. Demodulators often use periodic signals generated by NCOs as reference signals for locking onto the carrier wave during a demodulation process.
FIG. 1 is a simplified schematic of a known communication demodulator 100 incorporating an NCO 115, which generates a periodic signal used in a demodulation process. As shown, communication demodulator 100 receives a modulated data signal 120 carrying an information signal. The periodic signal generated by the NCO 115 and the modulated data signal are each received by a mixer-multiplier circuit 125 that separates the information signal from the modulated data signal 120. The output of the mixer-multiplier 125 is transmitted to a filter circuit 130 that filters out the carrier wave and outputs an information signal 135 (i.e., demodulated data).
FIG. 2 is a simplified schematic of NCO 115, showing the NCO in greater detail. NCO 115 is of a type commonly known and used in industry, and has numerous shortcomings that will be discussed. The NCO 115 includes a phase accumulator 205 for generating numerical sequences, such as memory addresses. In the phase accumulator a fixed number, called a phase increment 210, is summed with a delayed feedback number 215. The delayed feedback number 215 is controlled by a delay circuit 220 (e.g., a flip-flop) that clocks the delayed feedback number 215 into a modulo N adder 225. A system clock 230 provides clock pulses to the delay circuit for delaying the feedback. The numerical sequence output from the phase accumulator is then mapped to the desired periodic signal 235 (i.e., sine wave/sinusoidal signal) by peripheral logic 245 using a look-up table implemented in a memory 240, such as a read only memory (ROM). The memory 240 is configured to store a quarter of sine wave 235 in order to reduce memory size.
FIG. 3A shows a sine wave divided into quarter portions, such as those stored in memory 240. Although the memory 240 stores an incomplete sinusoid, peripheral logic 245 (see FIG. 2) provides for the full cycle of the sinusoid to be constructed. Consequently, the NCO is able to generate a single sinusoidal signal 235 as the desired output.
An additional signal, such as a quadrature signal (90xc2x0 out of phase), according to known NCO designs, requires a redundant memory for storing another sine wave quadrant and redundant peripheral logic for manipulating the other quadrant. FIG. 3B shows first and second sinusoidal signals 300 and 305. Sinusoidal signal (i.e., sine wave) 305 is said to be in quadrature with, or to be the quadrature signal of sinusoidal signal (i.e., cosine wave) 300.
FIG. 4 is a simplified schematic of a typical NCO 405 providing two sinusoidally varying signals 235a and 235b, with signal 235b being the quadrature signal of signal 235a. In order to generate the two signals, NCO 405 includes two memories 240a and 240b, and two peripheral logic circuits 245a and 245b. It is noted that a numeral scheme similar to that used in FIG. 2 is used for similar features shown in FIG. 4. Since NCO 405 requires redundant circuitry to generate the two signals 235a and 235b, the footprint (area occupied on a semiconductor chip) of the NCO 405 is relatively large. Alternatively, an additional output (i.e., signal 235b) may be generated with additional time-multiplexing circuitry (not shown), which tends to be costly and slow. For example, generating two sinusoidally varying signals from a single sinusoidally varying signal using time multiplexing techniques takes at least twice the amount of time required to generate a single sinusoidally varying signal. Further yet, known NCO 500 (see FIG. 5) providing multiple pairs of channel outputs 510 (each pair is labeled with a numerical suffix), require a pair of memories 520 (each pair is labeled with a numerical suffix) for each pair of channel outputs. Such NCO configurations requiring redundant systems and circuits are relatively costly to implement in multi-channel modulation and/or demodulation systems.
As can be understood from the above discussion, conventional NCOs use relatively large memories having relatively large footprints and relatively high cost to implement look-up tables for storage of quarter sine waves. Further, known multi-channel NCO designs add extra cost due to the use of redundant circuits. Accordingly the industry continues to strive to create low gate count (i.e., small footprint, low cost, low circuit redundancy), multi-channel NCOs for signal synthesis as well as other applications.
The present invention provides methods and apparatus for multi-channel output NCOs that do not engender the problems described above. NCOs characteristic of the present invention provide for reduced memory size and streamlined logic for implementing a high-speed and lower-power design with multi-channel outputs.
In accordance with an aspect of the present invention, a numerically controlled oscillator (NCO) comprises a phase accumulator configured to generate a periodic multi-bit signal at a given frequency; a first memory configured to store an octant of a sinusoidal waveform; a second memory configured to store a complementary octant of the sinusoidal waveform; and a control circuit, responsive to at least a portion of the phase accumulator signal and coupled to the first and second memories, the control circuit configured to access the first and second memories in parallel and construct respective sine and cosine waves at the given frequency. The invention can also be used to generate periodic waveforms other than sinusoidal, so long as the waveform has the symmetry property that the entire waveform can be reconstructed from a pair of complementary octants.
In some embodiments, the control circuit includes a memory address generator, responsive to a first subset of bits from the phase accumulator signal, configured to generate addresses for said first and second memories, said addresses providing for access in a normal sequence of increasing numerical values or access in a reverse sequence of decreasing numerical values; an octant-selector circuit, responsive to a second subset of bits from the phase accumulator signal, the octant-selector circuit being connected to receive outputs from the first and second memories and configured to use one of the first and second memory outputs to construct an unsigned-sine wave and to use the other of the first and second memory outputs to construct an unsigned-cosine wave; and a selective-negation circuit, responsive to a third subset of bits from the phase accumulator signal, the selective negation circuit being connected to receive the unsigned-sine wave and the unsigned-cosine wave from the octant-selector circuit and configured to generate the sine wave and the cosine wave therefrom.
In accordance with an aspect of the present invention, a method of operating a numerically controlled oscillator comprises generating a set of memory addresses and at least first, second, and third control bits in a phase accumulator, transmitting the memory addresses to first and second memories; storing in the first memory an octant of a sine wave; storing in the second memory another octant of a sine wave that is complementary to the octant stored in the first memory; transmitting from the first memory the octant in normal order or reverse order, transmitting from the second memory the other octant in normal order or reverse order; receiving the octant and other octant in a octant-selector circuit; outputting from the octant-selector circuit an unsigned-sine wave and an unsigned-cosine wave; and generating from the unsigned-sine wave and unsigned-cosine wave a sine wave and a cosine wave, respectively in a selective-negation circuit.
In some embodiments, the memory addresses are generated in ascending order and descending order; the first memory outputs the octant in normal order or reverse order in response to receiving the memory addresses in ascending order or descending order; and the second memory outputs the octant in normal order or reverse order in response to receiving the memory addresses in ascending order or descending order.
In accordance with an aspect of the present invention, a multi-channel numerical control oscillator comprises a plurality of phase accumulators configured to generate a plurality of memory addresses and a plurality of control bits; a multiplexer coupled to the plurality of phase accumulators, the multiplexer configured to receive output from the phase accumulators, and to selectively transmit the output of one of the phase accumulators; a channel select coupled to the multiplexer, the channel select configured to deliver a channel select signal to the multiplexer for controlling the multiplexer selective transmission; first and second memories coupled to the multiplexer, the first and second memories configured to receive memory addresses transmitted by the multiplexer, the first memory configured to store an octant of the sine wave, the second memory configured to store another octant of the sine wave, wherein the octants are complementary; a control circuit coupled to the first and second memories, the control circuit being configured to receive the octant from the first memory, to receive the other octant from the second memory, to construct a sine wave and a cosine wave, and selectively output to a first output one of the sine wave and the cosine wave and output to a second output the other of the sine wave and cosine wave; and a register back coupled to the control circuit, the register bank configured to receive the sine and cosine waves and selectively fan out the signal to a plurality of output channels, wherein the channel select is configured to deliver the channel select signal to the register bank for controlling selective fan out.
In accordance with an aspect of the present invention, a method of operating a numerically controlled oscillator comprises storing an octant of a sine wave; storing another octant of a sine wave that is complementary to the octant; generating a first set of memory addresses in ascending order, a second set of memory addresses in descending order, and a set of at least three control bits; transmitting the first or second memory addresses in response to one of the control bits; generating the octant and the other octant in normal or reverse order in response to receiving the first set of memory addresses or the second set of memory addresses; generating an unsigned-sine wave and an unsigned-cosine wave in response to receiving two of the control bits; and generating from the unsigned-sine wave and unsigned-cosine wave a sine wave and a cosine wave in response to the control bits.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.